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cy7c1470v33 cy7c1472v33 CY7C1474V33 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sram with nobl? architecture cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05289 rev. *s revised june 27, 2013 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sram with nobl? architecture features pin compatible and functionally equivalent to zbt supports 200 mhz bus operations with zero wait states ? available speed grades are 200 and 167 mhz internally self timed output buf fer control to eliminate the need to use asynchronous oe fully registered (inputs and outputs) for pipelined operation byte write capability single 3.3 v power supply 3.3 v/2.5 v i/o power supply fast clock-to-output time ? 3.0 ns (for 200 mhz device) clock enable (cen ) pin to suspend operation synchronous self timed writes cy7c1470v33 available in jedec-standard pb-free 100-pin tqfp, and non pb-free 165-ball fbga package. cy7c1472v33 available in jedec-standard pb-free 100-pin tqfp. CY7C1474V33 available in non pb-free 209-ball fbga package ieee 1149.1 jtag boundary scan compatible burst capability ? linear or interleaved burst order ?zz? sleep mode option and stop clock option functional description the cy7c1470v33, cy7c1472v33, and CY7C1474V33 are 3.3 v, 2 m 36/4 m 18/1 m 72 synchronous pipelined burst srams with no bus latency? (nobl ?? logic, respectively. they are designed to support unlimited true back-to-back read/write operations with no wait states. the cy7c1470v33, cy7c1472v33, and CY7C1474V33 are equipped with the advanced (nobl) logic required to enable consecutive read/write operations with data being transferred on every clock cycle. this feature dramatically improves the thro ughput of data in systems that require freq uent write/read transitions. the cy7c1470v33, cy7c1472v33, and CY7C1474V33 are pin compatible and functionally equivalent to zbt devices. all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation an d extends the previous clock cycle. write operations are controll ed by the byte write selects (bw a ?bw h for CY7C1474V33, bw a ?bw d for cy7c1470v33 and bw a ?bw b for cy7c1472v33) and a write enable (we ) input. all writes are conducted with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tristate c ontrol. in order to avoid bus contention, the output drivers are synchronously tristated during the data portion of a write sequence. selection guide description 200 mhz 167 mhz unit maximum access time 3.0 3.4 ns maximum operating current 500 450 ma maximum cmos standby current 120 120 ma errata: for information on silicon errata, see errata on page 34 . details include trigger conditions, devices affected, and proposed workaround
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 2 of 38 a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dq s dq p a dq p b dq p c dq p d d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s e c lk c en write drivers bw c bw d zz sleep control o u t p u t r e g i s t e r s logic block diagram ? cy7c1470v33 a0, a1, a c mode bw a bw b we ce1 ce2 ce3 oe read logic dq s dq p a dq p b d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e c lk c en write drivers zz sleep control logic block diagram ? cy7c1472v33
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 3 of 38 logic block diagra m ? CY7C1474V33 a0, a1, a c mode ce1 ce2 ce3 oe read logic dq s dq p a dq p b dq p c dq p d dq p e dq p f dq p g dq p h d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e c lk c en write drivers bw a bw b we zz sleep control bw c write registry and data coherency control logic bw d bw e bw f bw g bw h
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 4 of 38 contents pin configurations ........................................................... 5 pin definitions .................................................................. 8 functional overview ........................................................ 9 single read accesses ................................................ 9 burst read accesses .................................................. 9 single write accesses ................................................. 9 burst write accesses ................................................ 10 sleep mode ............................................................... 10 interleaved burst address tabl e ............................... 10 linear burst address table ....................................... 10 zz mode electrical characteri stics ............................ 10 truth table ...................................................................... 11 partial write cycle description ..................................... 12 partial write cycle description ..................................... 12 partial write cycle description ..................................... 13 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 14 disabling the jtag feature ...................................... 14 test access port (tap) ............................................. 14 performing a tap r eset .......... .............. .......... 14 tap registers ...................................................... 14 tap instruction set ................................................... 14 tap controller state diagram ....................................... 16 tap controller block diagram ...................................... 17 tap timing diagram ...................................................... 17 tap ac switching characteristics ............................... 18 3.3 v tap ac test conditions ....................................... 19 3.3 v tap ac output load equivalent ......................... 19 2.5 v tap ac test conditions ....................................... 19 2.5 v tap ac output load equivalent ......................... 19 tap dc electrical characteristics and operating conditions ..................................................... 19 identification register definitions ................................ 20 scan register sizes ....................................................... 20 identification codes ....................................................... 20 boundary scan exit order ...... ....................................... 21 boundary scan exit order ...... ....................................... 22 maximum ratings ........................................................... 23 operating range ............................................................. 23 neutron soft error immunity ......................................... 23 electrical characteristics ............................................... 23 capacitance .................................................................... 24 thermal resistance ........................................................ 24 ac test loads and waveforms ..................................... 25 switching characteristics .............................................. 26 switching waveforms .................................................... 27 ordering information ...................................................... 29 ordering code definitions ..... .................................... 29 package diagrams .......................................................... 30 acronyms ........................................................................ 33 document conventions ................................................. 33 units of measure ....................................................... 33 errata ............................................................................... 34 part numbers affected .............................................. 34 product status ........................................................... 34 ram9 sync/nobl zz pin issues errata summary .... 34 document history page ................................................. 35 sales, solutions, and legal information ...................... 38 worldwide sales and design s upport ......... .............. 38 products .................................................................... 38 psoc? solutions ...................................................... 38 cypress developer community ................................. 38 technical support ................. .................................... 38
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 5 of 38 pin configurations figure 1. 100-pin tqfp (14 20 1.4 mm) pinout [1] a a a a a 1 a 0 v ss v dd a a a a a a v ddq v ss dqb dqb dqb v ss v ddq dqb dqb v ss nc v dd dqa dqa v ddq v ss dqa dqa v ss v ddq v ddq v ss dqc dqc v ss v ddq dqc v dd v ss dqd dqd v ddq v ss dqd dqd dqd v ss v ddq a a ce 1 ce 2 bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz cy7c1470v33 a a a a a 1 a 0 v ss v dd a a a a a a a nc nc v ddq v ss nc dqpa dqa dqa v ss v ddq dqa dqa v ss nc v dd dqa dqa v ddq v ss dqa dqa nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dqb dqb v ss v ddq dqb dqb v dd v ss dqb dqb v ddq v ss dqb dqb dqpb nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode cy7c1472v33 bw d mode bw c dqc dqc dqc dqc dqpc dqd dqd dqd dqpb dqb dqa dqa dqa dqa dqpa dqb dqb (2 m 36) (4 m 18) bw b nc nc nc dqc nc nc(288) nc(144) a nc(288) nc(144) dqpd a a a a a note 1. errata: the zz pin (pin 64) needs to be externally connected to ground. for more information, see errata on page 34 .
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 6 of 38 figure 2. 165-ball fbga (15 17 1.4 mm) pinout [2] cy7c1470v33 (2 m 36) pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r tdo nc/576m nc/1g dqp c dq c dqp d nc dq d a ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc/144m nc v ddq v ss tms 891011 nc/288m a a adv/ld nc oe a a nc v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a note 2. errata: the zz ball (h11) needs to be externally connected to ground. for more information, see errata on page 34 .
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 7 of 38 figure 3. 209-ball fbga (14 22 1.76 mm) pinout [3] CY7C1474V33 (1 m 72) pin configurations (continued) a b c d e f g h j k l m n p r t u v w 12 34 56 789 11 10 dqg dqg dqg dqg dqg dqg dqg dqg dqc dqc dqc dqc nc dqpg dqh dqh dqh dqh dqd dqd dqd dqd dqpd dqpc dqc dqc dqc dqc nc dqh dqh dqh dqh dqph dqd dqd dqd dqd dqb dqb dqb dqb dqb dqb dqb dqb dqf dqf dqf dqf nc dqpf dqa dqa dqa dqa dqe dqe dqe dqe dqpa dqpb dqf dqf dqf dqf nc dqa dqa dqa dqa dqpe dqe dqe dqe dqe aaaa nc nc nc/144m a a nc/288m a aa aa a a1 a0 a aa aa a nc/576m nc nc nc nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc cen v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/1g v dd nc oe ce 3 ce 1 ce 2 adv/ld we v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ss v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq note 3. errata: the zz ball (p6) needs to be externally connected to ground. for more information, see errata on page 34 .
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 8 of 38 pin definitions pin name i/o type pin description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. bw a , bw b , bw c , bw d , bw e , bw f , bw g , bw h input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bw a controls dq a and dqp a , bw b controls dq b and dqp b , bw c controls dq c and dqp c , bw d controls dq d and dqp d , bw e controls dq e and dqp e , bw f controls dq f and dqp f , bw g controls dq g and dqp g , bw h controls dq h and dqp h . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst count er is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address. clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, the i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins. oe is masked during the da ta portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend the previous cycle when required. dq s i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip da ta register that is triggered by the rising edge of clk. as outputs, they deliver the da ta contained in the memory location specified by a [17:0] during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ?dq d are placed in a tristate condition. the outputs are automa tically tristated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp x i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq x . during write sequences, dqp a is controlled by bw a , dqp b is controlled by bw b , dqp c is controlled by bw c , and dqp d is controlled by bw d , dqp e is controlled by bw e , dqp f is controlled by bw f , dqp g is controlled by bw g , dqp h is controlled by bw h . mode input strap pin mode input . selects the burst order of the device. tied hi gh selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states durin g operation. when left floating mode will default high, to an interleaved burst order. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 9 of 38 functional overview the cy7c1470v33, cy7c1472v33, and CY7C1474V33 are synchronous-pipelined burst nobl srams designed specifically to eliminate wait states during write/read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . all data outputs pass through output registers controlled by the rising edge of the clock. maximum access dela y from the clock rise (t co ) is 3.0 ns (200 mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write oper ation, depending on the status of the write enable (we ). bw [x] can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and de selects) are pipelined. adv/ld should be driven low after the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory core and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. at the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.0 ns (200 mhz device) provided oe is active low. after the first clock of the read access the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. during the second clock, a subsequent operation (read/write/ deselect) can be initiated. deselecting the device is also pipelined. therefore, when the sram is deselected at clock rise by one of the chip enable signals, its output will tristate following the next clock rise. burst read accesses the cy7c1470v33, cy7c1472v 33, and CY7C1474V33 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read accesses section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap-around when incremented sufficiently. a high input on adv/ld will increment the internal burst counter regardless of the state of chip enables inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write accesses are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , tms test mode select synchronous this pin controls the test access port state machine . sampled on the rising edge of tck. tck jtag clock clock input to the jtag circuitry . v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . should be connected to ground of the system. nc ? no connects . this pin is not connected to the die. nc (144m, 288m, 576m, 1g) ? these pins are not connected . they will be used for expansion to the 144m, 288m, 576m, and 1g densities. zz [4] input- asynchronous zz ?sleep? input . this active high input places the device in a non-time critical ?sleep? condition with data integrity preserved. during normal operati on, this pin has to be low or left floating. zz pin has an internal pull-down. pin definitions (continued) pin name i/o type pin description note 4. errata: the zz pin needs to be externally connected to ground. for more information, see errata on page 34 .
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 10 of 38 and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address inputs is loaded into the address register. the write signals are latched into the control logic block. on the subsequent clock rise the data lines are automatically tristated regardless of the state of the oe input signal. this allows the external logic to present the data on dq and dqp (dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for CY7C1474V33, dq a,b,c,d /dqp a,b,c,d for cy7c1470v33 and dq a,b /dqp a,b for cy7c1472v33). in addition, the address for the subsequent access (read/write/deselect) is latched into the address register (provided the appropriate control signals are asserted). on the next clock rise the data presented to dq and dqp (dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for CY7C1474V33, dq a,b,c,d /dqp a,b,c,d for cy7c1470v33 and dq a,b /dqp a,b for cy7c1472v33) (or a subset for byte write operations, see write cycle description table for details) inputs is latched into the device and the write is complete. the data written during the writ e operation is controlled by bw (bw a,b,c,d,e,f,g,h for CY7C1474V33, bw a,b,c,d for cy7c1470v33 and bw a,b for cy7c1472v33) signals. the cy7c1470v33, cy7c1472v33, and CY7C1474V33 provides byte write capability that is described in the write cycle description table. asserting the write enable input (we ) with the selected byte write select (bw ) input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronous self timed write mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1470v33, cy7c1472v33, and CY7C1474V33 are common i/o devices, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dq and dqp (dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for CY7C1474V33, dq a,b,c,d /dqp a,b,c,d for cy7c1470v33 and dq a,b /dqp a,b for cy7c1472v33) inputs. doing so will tristate the output drivers. as a safety precaution, dq and dqp (dq a,b,c,d,e,f,g,h /dqp a,b,c,d,e,f,g,h for CY7C1474V33, dq a,b,c,d /dqp a,b,c,d for cy7c1470v33 and dq a,b /dqp a,b for cy7c1472v33) are automatically tristated during the data portion of a write cycle, regardless of the state of oe . burst write accesses the cy7c1470v33, cy7c1472v33, and CY7C1474V33 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write op erations without reasserting the address inputs. adv/ld must be driven low in order to load the initial address, as described in the single write accesses section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the bur st counter is incremented. the correct bw (bw a,b,c,d,e,f,g,h for CY7C1474V33, bw a,b,c,d for cy7c1470v33 and bw a,b for cy7c1472v33) inputs must be driven in each cycle of the burst wr ite in order to write the correct bytes of data. sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data inte grity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1:a0 second address a1:a0 third address a1:a0 fourth address a1:a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz ? v dd ?? 0.2 v ? 120 ma t zzs device operation to zz zz ?? v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz ? 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curr ent this parameter is sampled 0 ? ns
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 11 of 38 truth table the truth table for parts cy7c1470v33/cy 7c1472v33/CY7C1474V33 is as follows. [5, 6, 7, 8, 9, 10, 11] operation address used ce zz adv/ld we bw x oe cen clk dq deselect cycle none h l l x x x l l?h tri-state continue deselect cycle none x l h x x x l l?h tri-state read cycle (begin burst) external l l l h x l l l?h data out (q) read cycle (continue burst) n ext x l h x x l l l?h data out (q) nop/dummy read (begin burst) e xternal l l l h x h l l?h tri-state dummy read (continue burst) next x l h x x h l l?h tri-state write cycle (begin burst) external l l l l l x l l?h data in (d) write cycle (continue burst) next x l h x l x l l?h data in (d) nop/write abort (begin bur st) none l l l l h x l l?h tri-state write abort (continue burst ) next x l h x h x l l?h tri-state ignore clock edge (stall) current x l x x x x h l?h ? sleep mode none xh x xxxx x tri-state notes 5. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = 0 signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 6. write is defined by we and bw [a:d] . see write cycle description table for details. 7. when a write cycle is detected, all i/os are tristated, even during byte writes. 8. the dq and dqp pins are controlled by the current cycle and the oe signal. 9. cen = h inserts wait states. 10. device will power-up deselected and the i/os in a tristate condition, regardless of oe . 11. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dq s and dqp [a:d] = tristate when oe is inactive or when the device is deselected, and dq s = data when oe is active.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 12 of 38 partial write cycle description the partial write cycle description fo r part cy7c1470v33 is as follows. [12, 13, 14, 15] function (cy7c1470v33) we bw d bw c bw b bw a read h x x x x write ? no bytes written l h h h h write byte a ? (dq a and dqp a )lhhhl write byte b ? (dq b and dqp b )lhhlh write bytes b, a l h h l l write byte c ? (dq c and dqp c )lhlhh write bytes c, a l h l h l write bytes c, b l h l l h write bytes c, b, a l h l l l write byte d ? (dq d and dqp d )llhhh write bytes d, a l l h h l write bytes d, b l l h l h write bytes d, b, a l l h l l write bytes d, c l l l h h write bytes d, c, a l l l h l write bytes d, c, b l l l l h write all bytes lllll partial write cycle description the partial write cycle description fo r part cy7c1472v33 is as follows. [12, 13, 14, 15] function (cy7c1472v33) we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l notes 12. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = 0 signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 13. write is defined by we and bw [a:d] . see write cycle description table for details. 14. when a write cycle is detected, all i/os are tristated, even during byte writes. 15. table only lists a partial listing of the byte write combinations. any combination of bw [a:d] is valid. appropriate write will be done based on which byte write is active.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 13 of 38 partial write cycle description the partial write cycle description fo r part CY7C1474V33 is as follows. [16, 17, 18, 19] function (CY7C1474V33) we bw x read h x write ? no bytes written l h write byte x ??? (dq x and dqp x) ll write all bytes l all bw = l notes 16. x = ?don't care?, h = logic high, l = logic low, ce stands for all chip enables active. bw x = 0 signifies at least one byte write select is active, bw x = valid signifies that the desired byte write selects are asserted, see write cycle description table for details. 17. write is defined by we and bw [a:d] . see write cycle description table for details. 18. when a write cycle is detected, all i/os are tristated, even during byte writes. 19. table only lists a partial listing of the byte write combinations. any combination of bw [a:d] is valid. appropriate write will be done based on which byte write is active.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 14 of 38 ieee 1149.1 serial boundary scan (jtag) the cy7c1470v33, and cy7c14 74v33 incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specific ation are excluded because their inclusion places an added delay in the critical speed path of the sram. note that the tap controller functions in a manner that does not conflict with the operat ion of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 3.3 v or 2.5 v i/o logic levels. the cy7c1470v33, and CY7C1474V33 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap co ntroller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are internally pulled up and may be unconnected. they may alternately be connected to v dd through a pull up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which wil l not interfere with the operation of the device. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information on loading the instruction register, see the tap controller state diagram on page 16 . tdi is internally pulled up and can be unconnected if the tap is unus ed in an application. tdi is connected to the most signific ant bit (msb) of any register. test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is active depending upon the current state of the tap state machine (see identification codes on page 20 ). the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does no t affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected betw een the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 17 . upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in th e capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the board-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the by pass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the boundary scan register is loaded with the contents of the ram i/o ring when the tap controll er is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan exit order on page 21 and boundary scan exit order on page 22 show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the re gister is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regist er has a vendor code and other information described in the identif ication register definitions table. tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in identification
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 15 of 38 codes on page 20 . three of these instructions are listed as reserved and should not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a captur e of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction after it is shifted in, the tap controller needs to be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction which is to be executed whenever the instruction r egister is loaded with all 0s. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-0 instruction. when an extest instruction is loaded into the instruction register, the sram respond s as if a sample/preload instruction has been loaded. there is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high z state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction causes the boundary scan register to be connected between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output will undergo a transition. the tap may then tr y to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/preload instruction. if th is is an issue, it is still possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that since the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction will have the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 16 of 38 tap controller state diagram the 0/1 next to each state represents t he value of tms at the rising edge of tck. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 17 of 38 tap controller block diagram tap timing diagram bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 18 of 38 tap ac switchi ng characteristics over the operating range parameter [20, 21] description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns notes 20. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 21. test conditions are spec ified using the load in tap ac test conditions. t r /t f = 1 ns.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 19 of 38 3.3 v tap ac test conditions input pulse levels ...............................................v ss to 3.3 v input rise and fall times ...................................................1 ns input timing reference levels .. ....................................... 1.5 v output reference levels ................................................ 1.5 v test load termination supply voltage ............................ 1.5 v 3.3 v tap ac out put load equivalent 2.5 v tap ac test conditions input pulse levels ............ ................................... v ss to 2.5 v input rise and fall time ....................................................1 ns input timing reference levels ... .................................... 1.25 v output reference levels .............................................. 1.25 v test load termination supply vo ltage .......................... 1.25 v 2.5 v tap ac output load equivalent tdo 1.5v 20pf z = 50 o 50 tdo 1.25v 20pf z = 50 o 50 (0 c < t a < +70 c; v dd = 3.135 v to 3.6 v unless otherwise noted) parameter [22] description test conditions min max unit v oh1 output high voltage i oh = ?4.0 ma,v ddq = 3.3 v 2.4 ? v i oh = ?1.0 ma,v ddq = 2.5 v 2.0 ? v v oh2 output high voltage i oh = ?100 a v ddq = 3.3 v 2.9 ? v v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 8.0 ma v ddq = 3.3 v ? 0.4 v i ol = 1.0 ma v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 3.3 v ? 0.2 v v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 3.3 v 2.0 v dd + 0.3 v v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 3.3 v ?0.3 0.8 v v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd < v in < v ddq ?5 5 a note 22. all voltages referenced to v ss (gnd).
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 20 of 38 identification regi ster definitions instruction field cy7c1470v33 (2 m 36) CY7C1474V33 (1 m 72) description revision number (31:29) 000 000 describes the version number device depth (28:24) [23] 01011 01011 reserved for internal use architecture/memory type (23:18) 001000 00100 0 defines memory type and architecture bus width/density (17:12) 100100 110100 defines width and density cypress jedec id code (11:1) 00000110100 0000011 0100 allows unique identification of sram vendor id register presence indicator (0) 1 1 indicates the presence of an id register scan register sizes register name bit size ( 36) bit size ( 72) instruction 3 3 bypass 11 id 32 32 boundary scan order ? 165-ball fbga 71 ? boundary scan order ? 209-ball fbga ? 110 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high z state. this instruction is not 1149.1 compliant. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. places th e boundary scan register between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. places the boundary scan register between tdi and tdo. does not affect sram operation. this instructio n does not implement 1149.1 preload function and is therefore not 1149.1 compliant. reserved 101 do not use: this instruct ion is reserved for future use. note 23. bit #24 is ?1? in the id register definitions for both 2.5 v and 3.3 v versions of this device.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 21 of 38 boundary scan exit order (2 m 36) bit # 165-ball id bit # 165-ball id bit # 165-ball id bit # 165-ball id 1c1 21r3 41j11 61b7 2d1 22p2 42k10 62b6 3 e1 23 r4 43 j10 63 a6 4d2 24p6 44h11 64b5 5e2 25r6 45g11 65a5 6f1 26r8 46f11 66a4 7g1 27p3 47e11 67b4 8f2 28p4 48d10 68b3 9g2 29p8 49d11 69a3 10 j1 30 p9 50 c11 70 a2 11 k1 31 p10 51 g10 71 b2 12 l1 32 r9 52 f10 13 j2 33 r10 53 e10 14 m1 34 r11 54 a9 15 n1 35 n11 55 b9 16 k2 36 m11 56 a10 17 l2 37 l11 57 b10 18 m2 38 m10 58 a8 19 r1 39 l10 59 b8 20 r2 40 k11 60 a7
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 22 of 38 boundary scan exit order (1 m 72) bit # 209-ball id bit # 209-ball id bit # 209-ball id bit # 209-ball id 1a1 29t1 57u10 85b11 2a2 30t2 58t11 86b10 3b1 31u1 59t10 87a11 4b2 32u2 60r11 88a10 5c1 33v1 61r10 89a7 6c2 34v2 62p11 90a5 7d1 35w1 63p10 91a9 8d2 36w2 64n11 92u8 9e1 37t6 65n10 93a6 10 e2 38 v3 66 m11 94 d6 11 f1 39 v4 67 m10 95 k6 12 f2 40 u4 68 l11 96 b6 13 g1 41 w5 69 l10 97 k3 14 g2 42 v6 70 p6 98 a8 15 h1 43 w6 71 j11 99 b4 16 h2 44 v5 72 j10 100 b3 17 j1 45 u5 73 h11 101 c3 18 j2 46 u6 74 h10 102 c4 19 l1 47 w7 75 g11 103 c8 20 l2 48 v7 76 g10 104 c9 21 m1 49 u7 77 f11 105 b9 22 m2 50 v8 78 f10 106 b8 23 n1 51 v9 79 e10 107 a4 24 n2 52 w11 80 e11 108 c6 25 p1 53 w10 81 d11 109 b7 26 p2 54 v11 82 d10 110 a3 27 r2 55 v10 83 c11 28 r1 56 u11 84 c10
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 23 of 38 maximum ratings exceeding maximum ratings may shorten the useful life of the device. user guidelines are not tested. storage temperature .. ............... ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage on v dd relative to gnd .......?0.5 v to +4.6 v supply voltage on v ddq relative to gnd ...... ?0.5 v to +v dd dc to outputs in tri-state ...................?0.5 v to v ddq + 0.5 v dc input voltage .............. .............. ..... ?0.5 v to v dd + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (per mil-std-883, method 3015) .......................... > 2001 v latch-up current .................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 c to +70 c 3.3 v ? ? 5% / + 10% 2.5 v ? 5% to v dd industrial ?40 c to +85 c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single bit upsets 25 c 361 394 fit/ mb lmbu logical multi bit upsets 25 c 0 0.01 fit/ mb sel single event latch-up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculat ion. for more details refer to application note an54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates? . electrical characteristics over the operating range parameter [24, 25] description test conditions min max unit v dd power supply voltage 3.135 3.6 v v ddq i/o supply voltage for 3.3 v i/o 3.135 v dd v for 2.5 v i/o 2.375 2.625 v v oh output high voltage for 3.3 v i/o, i oh = ?? 4.0 ma 2.4 ? v for 2.5 v i/o, i oh = ?? 1.0 ma 2.0 ? v v ol output low voltage for 3.3 v i/o, i ol = ? 8.0 ma ? 0.4 v for 2.5 v i/o, i ol = ? 1.0 ma ? 0.4 v v ih input high voltage [24] for 3.3 v i/o 2.0 v dd + 0.3 v for 2.5 v i/o 1.7 v dd + 0.3 v v il input low voltage [24] for 3.3 v i/o ?0.3 0.8 v for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ? 5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ? 30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a notes 24. overshoot: v ih(ac) < v dd +1.5 v (pulse width less than t cyc /2), undershoot: v il(ac) > ?2 v (pulse width less than t cyc /2). 25. t power up : assumes a linear ramp from 0 v to v dd(min) within 200 ms. during this time v ih < v dd and v ddq < v dd .
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 24 of 38 i dd v dd operating supply v dd = max, i out = 0 ma, f = f max = 1/t cyc 5.0 ns cycle, 200 mhz ?500ma 6.0 ns cycle, 167 mhz ? 450 ma i sb1 automatic ce power-down current ? ttl inputs max v dd , device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc 5.0 ns cycle, 200 mhz ?245ma 6.0 ns cycle, 167 mhz ? 245 ma i sb2 automatic ce power-down current ? cmos inputs max v dd , device deselected, v in ? 0.3 v or v in > v ddq ?? 0.3 v, f = 0 all speed grades ? 120 ma i sb3 automatic ce power-down current ? cmos inputs max v dd , device deselected, v in ? 0.3 v or v in > v ddq ?? 0.3 v, f = f max = 1/t cyc 5.0 ns cycle, 200 mhz ?245ma 6.0 ns cycle, 167 mhz ? 245 ma i sb4 automatic ce power-down current ? ttl inputs max v dd , device deselected, v in ? v ih or v in ? v il , f = 0 all speed grades ? 135 ma electrical characteristics (continued) over the operating range parameter [24, 25] description test conditions min max unit capacitance parameter [26] description test conditions 100-pin tqfp max 165-ball fbga max 209-ball fbga max unit c address address input capacitance t a = 25 ? c, f = 1 mhz, v dd = 3.3 v, v ddq = 2.5 v 6 6 6 pf c data data input capacitance 5 5 5 pf c ctrl control input capacitance 8 8 8 pf c clk clock input capacitance 6 6 6 pf c i/o input/output capacitance 5 5 5 pf thermal resistance parameter [26] description test conditions 100-pin tqfp package 165-ball fbga package 209-ball fbga package unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 24.63 16.3 15.2 ? c/w ? jc thermal resistance (junction to case) 2.28 2.1 1.7 ? c/w note 26. tested initially and after any design or proces s changes that may affect these parameters.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 25 of 38 ac test loads and waveforms figure 4. ac test loads and waveforms output r = 317 ? r = 351 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.5 v 3.3 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 3.3 v i/o test load output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 2.5 v i/o test load
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 26 of 38 switching characteristics over the operating range parameter [27, 28] description -200 -167 unit min max min max t power [29] v cc(typical) to the first access read or write 1 ? 1 ? ms clock t cyc clock cycle time 5.0 ? 6.0 ? ns f max maximum operating frequency ? 200 ? 167 mhz t ch clock high 2.0 ? 2.2 ? ns t cl clock low 2.0 ? 2.2 ? ns output times t co data output valid after clk rise ? 3.0 ? 3.4 ns t oev oe low to output valid ? 3.0 ? 3.4 ns t doh data output hold after clk rise 1.3 ? 1.5 ? ns t chz clock to high z [30, 31, 32] ? 3.0 ? 3.4 ns t clz clock to low z [30, 31, 32] 1.3 ? 1.5 ? ns t eohz oe high to output high z [30, 31, 32] ? 3.0 ? 3.4 ns t eolz oe low to output low z [30, 31, 32] 0 ? 0 ? ns setup times t as address setup before clk rise 1.4 ? 1.5 ? ns t ds data input setup before clk rise 1.4 ? 1.5 ? ns t cens cen setup before clk rise 1.4 ? 1.5 ? ns t wes we , bw x setup before clk rise 1.4 ? 1.5 ? ns t als adv/ld setup before clk rise 1.4 ? 1.5 ? ns t ces chip select setup 1.4 ? 1.5 ? ns hold times t ah address hold after clk rise 0.4 ? 0.5 ? ns t dh data input hold after clk rise 0.4 ? 0.5 ? ns t cenh cen hold after clk rise 0.4 ? 0.5 ? ns t weh we , bw x hold after clk rise 0.4 ? 0.5 ? ns t alh adv/ld hold after clk rise 0.4 ? 0.5 ? ns t ceh chip select hold after clk rise 0.4 ? 0.5 ? ns notes 27. timing reference is 1.5 v when v ddq = 3.3 v and is 1.25 v when v ddq = 2.5 v. 28. test conditions shown in (a) of figure 4 on page 25 unless otherwise noted. 29. this part has a voltage regulator internally; t power is the time power needs to be supplied above v dd(minimum) initially, before a read or write operation can be initiated. 30. t chz , t clz , t eolz , and t eohz are specified with ac test conditions shown in (b) of figure 4 on page 25 . transition is measured 200 mv from steady-state voltage. 31. at any voltage and temperature, t eohz is less than t eolz and t chz is less than t clz to eliminate bus contention between sr ams when sharing the same data bus. these specifications do not imply a bus c ontention condition, but reflect parameters guaranteed over worst case user conditions . device is designed to achieve high z prior to low z under the same system conditions. 32. this parameter is sampled and not 100% tested.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 27 of 38 switching waveforms figure 5. read/write/timing [33, 34, 35] write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds data i n-out (dq) t clz d(a1) d(a2) d(a5) q(a4) q(a3) d(a2+1) t doh t chz t co write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz t doh dont care undefined q(a6) q(a4+1) notes 33. for this waveform zz is tied low. 34. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 35. order of the burst sequence is determined by the status of th e mode (0 = linear, 1= interleaved). burst operations are optio nal.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 28 of 38 figure 6. nop, stall and deselect cycles [36, 37, 38] figure 7. zz mode timing [39, 40] switching waveforms (continued) read q(a3) 456 78910 clk ce we cen bwx adv/ld address a3 a4 a5 d(a4) data in-out (dq) a1 q(a5) write d(a4) stall write d(a1) 123 read q(a2) stall nop read q(a5) deselect continue deselect dont care undefined t chz a2 d(a1) q(a2) q(a3) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 36. for this waveform zz is tied low. 37. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 38. the ignore clock edge or stall cycle (clock 3) illustrated cen being used to create a pause. a write is not performed during this cycle. 39. device must be deselected when entering zz mode. see cycle descr iption table for all possible signal conditions to deselect the device. 40. i/os are in high z when exiting zz sleep mode.
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 29 of 38 ordering information the table below contains only the parts that are currently availa ble. if you don?t see what you are looking for, please contact your local sales representative. for more inform ation, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypre ss.com/products cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices ordering code definitions speed (mhz) ordering code package diagram part and package type operating range 167 cy7c1470v33-167axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1470v33-167bzc 51-85165 165- ball fbga (15 17 1.4mm) CY7C1474V33-167bgc 51-85167 209-ball fbga (14 22 1.76 mm) cy7c1470v33-167axi 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free lndustrial cy7c1470v33-167bzi 51-85165 165- ball fbga (15 17 1.4mm) 200 cy7c1470v33-200axc 51-85050 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1472v33-200axc CY7C1474V33-200bgc 51-85167 209-ball fbga (14 22 1.76 mm) cy7c1470v33-200bzi 51-85165 165-ball fbga (15 17 1.4mm) lndustrial temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = a or bz or bg a = 100-pin tqfp bz = 165-ball fbga bg = 209-ball fbga speed grade: xxx = 167 mhz or 200 mhz v33 = 3.3 v 147x = 1470 or 1472 or 1474 1470 = pl, 2 mb 36 (72 mb) 1472 = pl, 4 mb 18 (72 mb) 1474 = pl, 1 mb 72 (72 mb) technology code: c = cmos marketing code: 7 = sram company id: cy = cypress x c147xv33 - xxx xx cy 7 x
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 30 of 38 package diagrams figure 8. 100-pin tqfp (14 20 1.4 mm) a100ra package outline, 51-85050 51-85050 *d
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 31 of 38 figure 9. 165-ball fbga (15 17 1.40 mm) (0.45 ball diameter) package outline, 51-85165 package diagrams (continued) 51-85165 *d
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 32 of 38 figure 10. 209-ball fbga (14 22 1.76 mm) bb209a package outline, 51-85167 package diagrams (continued) 51-85167 *c
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 33 of 38 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor ce chip enable cen clock enable fbga fine-pitch ball grid array i/o input/output jtag joint test action group nobl no bus latency oe output enable sram static random access memory tck test clock tdi test data input tms test mode select tdo test data output tqfp thin quad flat pack we write enable symbol unit of measure c degree celsius mhz megahertz a microampere ma milliampere mm millimeter ms millisecond ns nanosecond pf picofarad vvolt wwatt
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 34 of 38 errata this section describes the ram9 sync/nobl zz pin issues. de tails include trigger conditions, the devices affected, proposed workaround and silicon revision applicability. please contact your local cypress sales representative if you have further quest ions. part numbers affected product status all of the devices in the ram9 72mb sync/nobl family are qualified and available in production quantities. ram9 sync/nobl zz pin issues errata summary the following table defines the errata applicable to available ram9 72mb sync/nobl family devices. 1. zz pin issue problem definition the problem occurs only when the device is operated in the no rmal mode with zz pin left floating. the zz pin on the sram device does not have an internal pull-do wn resistor. switching noise in the system may cause the sram to recognize a high on the zz input, which may cause the sram to enter sleep mode. this could result in incorrect or undesirable operation of the sram. trigger conditions device operated with zz pin left floating. scope of impact when the zz pin is left floating, the device delivers incorrect data. workaround tie the zz pin externally to ground. fix status fix was done for the 72mb ram9 synchronous srams and 72m ram9 nobl srams devices. fixed devices have a new revision. the following table lists the devices affected and the new revision after the fix. density & revision package type operating range 72mb-ram9 nobl srams: cy7c147*, cy7c147*v33 all packages commercial/ industrial item issues description device fix status 1. zz pin when asserted high, the zz pin places device in a ?sleep? condition with data integrity preserved.the zz pin currently does not have an internal pull-down resistor and hence cannot be left floating externally by the user during normal mode of operation. 72m-ram9 (90nm) for the 72m ram9 (90 nm) devices, this issue was fixed in the new revision. please contact your local sales rep for availability. table 1. list of affected devices and the new revision revision before the fix new revision after the fix cy7c147* cy7c147*b cy7c147*v33 cy7c147*bv33
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 35 of 38 document history page document title: cy7c1470v33/cy7c1472v3 3/CY7C1474V33, 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sram with nobl? architecture document number: 38-05289 rev. ecn submission date orig. of change description of change ** 114676 08/06/02 pks new data sheet. *a 121520 01/27/03 cjm changed status from advanced information to preliminary. updated features (for package offering, removed 300 mhz frequency related information). updated selection guide (removed 300 mhz frequency related information). updated functional overview (removed 300 mhz frequency related information). updated electrical characteristics (removed 300 mhz frequency related information). updated switching characteristics (removed 300 mhz frequency related information, changed maximum value of t co , t eov , t chz , t eohz parameters from 2.4 ns to 2.6 ns for 250 mhz frequency, changed minimum value of t doh , t clz parameters from 0.8 ns to 1.0 ns for 250 mhz frequency, changed minimum value of t doh , t clz parameters from 1.0 ns to 1.3 ns for 200 mhz frequency). updated ordering information (updated part numbers). *b 223721 see ecn njy updated features (removed 250 mhz frequency related information and included 225 mhz frequency related information). updated functional description (description). updated logic block diagram (splitted logic block diagram into three logic block diagrams). updated functional overview (description). updated boundary scan exit order (replaced tbd with values for all packages). updated electrical characteristics (removed 250 mhz frequency related information and included 225 mhz frequency related information, replaced tbd with values for maximum values of i dd , i sb1 , i sb2 , i sb3 , i sb4 parameters). updated capacitance (replaced tbd with values for all packages). updated thermal resistance (replaced tbd with values for all packages). updated switching characteristics (removed 250 mhz frequency related information and included 225 mhz frequency related information). updated switching waveforms . updated package diagrams (spec 51-85165 (changed revision from ** to *a) for 165-ball fbga package, removed 119-ball bga package (spec 51-85115), removed spec 51-85143 and incluuded spec 51-85167 for 209-ball bga package). *c 235012 see ecn ryq minor change (to match on the spec system and external web). *d 243572 see ecn njy updated pin configurations (updated figure 2 (changed ball c11, d11, e11, f11, g11 from dqp b , dq b , dq b , dq b , dq b to dqp a , dq a , dq a , dq a , dq a (corresponding to cy7c1472v33))). updated capacitance (splitted c in parameter into c address , c data , c clk parameters and also updated the values).
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 36 of 38 *e 299511 see ecn syt / vbl updated features (removed 225 mhz frequency related information and included 250 mhz frequency related information). updated selection guide (removed 225 mhz frequ ency related information and included 250 mhz frequency related information). updated electrical characteristics (removed 225 mhz frequency related information and included 250 mhz frequency related information). updated thermal resistance (changed value of ? ja from 16.8 ? c/w to 24.63 ? c/w, and changed value of ? jc from 3.3 ? c/w to 2.28 ? c/w for 100-pin tqfp package). updated switching characteristics (removed 225 mhz frequency related information and included 250 mhz frequency related information, changed minimum value of t cyc from 4.4 ns to 4.0 ns for 250 mhz frequency). updated ordering information (updated part numbers (removed 225 mhz frequency related information and included 250 mhz frequency related information, added pb-free information for 100-pin tqfp package and 165-ball fbga package, added industria l temperature range part numbers), added comment of ?pb-free bg package s availability? below the ordering information). *f 323039 see ecn pci changed status from preliminary to final. updated selection guide (unshaded 250 mhz frequency related information). updated pin configurations (address expansion pins/balls in the pinouts for all packages are modified as per jedec standard, updated figure 3 (changed package name from 209-ball pbga to 209-ball fbga)). updated pin definitions (added address expansion pins). updated electrical characteristics (updated test conditions of v ol , v oh parameters, unshaded 250 mhz frequency related information). updated switching characteristics (unshaded 250 mhz frequency related information). updated ordering information (updated part numbers, unshaded all shaded areas, removed comment of ?pb-free bg packages availability? below the ordering information). *g 351937 see ecn pci updated ordering information (updated part numbers). *h 416221 see ecn rxu changed address of cypre ss semiconductor corporation from ?3901 north first street? to ?198 champion court?. updated electrical characteristics (updated note 25 (changed v ddq < v dd to v ddq < v dd ), changed description of i x parameter from input load current except zz and mode to input leak age current except zz and mode, changed minimum value of i x parameter (corresponding to input current of mode (input = v ss )) from ?5 a to ?30 a, changed maximum value of i x parameter (corresponding to inpu t current of mode (input = v dd )) from 30 a to 5 a, changed minimum value of i x parameter (corresponding to input current of zz (input = v ss )) from ?30 a to ?5 a, changed maximum value of i x parameter (corresponding to input current of zz (input = v dd )) from 5 a to 30 a). updated ordering information (updated part numbers, replaced package name column with package diagram in the ordering information table). replaced three-state with tri-state in all instances across the document. document history page (continued) document title: cy7c1470v33/cy7c1472v3 3/CY7C1474V33, 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sram with nobl? architecture document number: 38-05289 rev. ecn submission date orig. of change description of change
cy7c1470v33 cy7c1472v33 CY7C1474V33 document number: 38-05289 rev. *s page 37 of 38 *i 472335 see ecn vkn updated pin configurations (updated figure 3 (corrected the ball name for h9 from v ssq to v ss ). updated tap ac switching characteristics (changed minimum value of t th , t tl parameters from 25 ns to 20 ns, changed maximum value of t tdov parameter from 5 ns to 10 ns). updated maximum ratings (added maximum rating for supply voltage on v ddq relative to gnd). updated ordering information (updated part numbers). *j 2756998 08/28/09 vkn added neutron soft error immunity . updated ordering information (updated part numbers (i ncluding parts that are available), and modified the disclaimer for the ordering information). updated package diagrams (spec 51-85165 (changed revision from *a to *b)). *k 2903057 04/01/2010 njy updated ordering information (updated part numbers). updated package diagrams . *l 3033272 09/19/2010 njy added ordering code definitions . added acronyms and units of measure . minor edits and updated in new template. *m 3052882 10/08/2010 njy updated ordering information (removed obsolete parts). *n 3357114 08/29/2011 prit updated package diagrams . *o 3403584 10/12/2011 prit updated ordering information (removed prune part number cy7c1472v33-167axi). updated package diagrams . *p 3638614 06/06/2012 prit updated features (removed 250 mhz frequency related information, removed 165-ball fbga package related information (corresponding to cy7c1472v33)). updated selection guide (removed 250 mhz frequency related information). updated pin configurations (updated figure 2 (removed cy7c1472v33 related info rmation)). updated functional overview (removed 250 mhz frequency related information). updated ieee 1149.1 serial boundary scan (jtag) (removed cy7c1472v33 related information). updated identification register definitions (removed cy7c1472v33 related information). updated scan register sizes (removed ?bit size ( 18)? column). removed boundary scan exit order (corresponding to cy7c1472v33). updated electrical characteristics (removed 250 mhz frequency related information). updated switching characteristics (removed 250 mhz frequency related information). updated ordering information (updated part numbers). *q 3755966 09/26/2012 prit updated package diagrams (spec 51-85167 (changed revision from *b to *c)). *r 3971410 04/18/2013 prit updated ordering information (updated part numbers). added errata . *s 4042037 06/27/2013 prit added errata footnotes. updated in new template. document history page (continued) document title: cy7c1470v33/cy7c1472v3 3/CY7C1474V33, 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sram with nobl? architecture document number: 38-05289 rev. ecn submission date orig. of change description of change
document number: 38-05289 rev. *s revised june 27, 2013 page 38 of 38 nobl tm and no bus latency tm are trademarks of cypress semiconductor corporation. all products and company names mentioned in this document may be the trad emarks of their respective holders. cy7c1470v33 cy7c1472v33 CY7C1474V33 ? cypress semiconductor corporation, 2002-2013. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support cypress.com/go/support

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